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Title:
CERAMIC COMPOSITION BAKED AT LOW TEMPERATURE AND MULTI- LAYER WIRING BOARD USING IT
Document Type and Number:
Japanese Patent JP2002167274
Kind Code:
A
Abstract:

To provide a ceramic composition baked at a low temperature capable of baking coincidently with a low resistant conductor such as copper or silver, with a high specific dielectric constant, low tan δ, and a small absolute value of the changing ratio of the specific dielectric constant by temperature change, and provide multi-layer wiring board using it for a part of insulating substrate.

The low temperature sintered ceramic composition containing SiO2 of 10-30 wt.%, MgO of 1-10 wt.%, CaO of 5-15 wt.%, TiO2 of 15-30 wt.% and La2O3 of 5-25 wt.%, with the specific dielectric constant of ≥14 at 1 MHz-3 GHz, dielectric loss of ≤50×10-4, the absolute value of the changing ratio of the dielectric constant by the temperature change of ≤100×10-6/°C at -40-85°C, and is used for inside insulating layer 1b of the multi-layer wiring board. On both the upper/lower faces of the insulator layer 1b the electrodes 3, 3 are formed and provides a built in capacitor in the multi-layer wiring board.


Inventors:
NAKAO YOSHIHIRO
SUZUKI SHINICHI
NAGAE KENICHI
KIMURA TETSUYA
KOKUBU MASAYA
Application Number:
JP2000363716A
Publication Date:
June 11, 2002
Filing Date:
November 29, 2000
Export Citation:
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Assignee:
KYOCERA CORP
International Classes:
C04B35/22; C04B35/195; C04B35/46; C04B35/49; H01B3/12; H05K3/46; (IPC1-7): C04B35/46; C04B35/195; C04B35/22; C04B35/49; H01B3/12; H05K3/46
Domestic Patent References:
JPH07272537A1995-10-20
JPH0873239A1996-03-19
JPH08259264A1996-10-08
JPH06215629A1994-08-05
JPH07272537A1995-10-20
JPH0873239A1996-03-19
JPH08259264A1996-10-08
JPH06215629A1994-08-05