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Title:
CHANNEL CONTROL SYSTEM
Document Type and Number:
Japanese Patent JP2779096
Kind Code:
B2
Abstract:

PURPOSE: To cancel the suppression of interruptions without affecting the selec tion processing of channel paths even if plural interruptions are suppressed at one time by canceling the suppression of interruptions through an input/output processor.
CONSTITUTION: A channel controller 10 inquires of a channel processor 2 about an interruption when an interruption is received from an input/output device 40. Then, the controller 10 gives an interruption suppressing instruction to the device 40 when this instruction is received from the processor 20. At the same time, the device 40 of which interruption has been suppressed is stored in a work memory part 102 of the controller 10. Then, the time is monitored by a timer 101 and the information on the device 40 is taken out of the part 102, and the reference is given to the state information 60 on the device 40 stored in a main storage 6. Then, an interruption suppression canceling instruction is given to the device 40 when as the interruption factor is canceled.


Inventors:
Shigeno, Takeshi
Morikawa, Takashi
Application Number:
JP1992000186919
Publication Date:
July 23, 1998
Filing Date:
July 14, 1992
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F13/12; (IPC1-7): G06F13/12
Domestic Patent References:
JP6175949A
Attorney, Agent or Firm:
武 顕次郎



 
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