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Patent Searching and Data


Title:
CHANNEL CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS6037053
Kind Code:
A
Abstract:

PURPOSE: To decrease the number of asynchronous interruption by performing control so as to send device numbers to an input/output processor while a channel device is performing the processing related to the error information, etc. of a certain device.

CONSTITUTION: When a channel device 2 is performing the processing related to the error information, etc. of a certain device, a register PDNR21 is turned on to send its output signal to an input/output processor 3. In this case, if an asynchronous interruption request is supplied to the processor 3 from a device (#0)4, an asynchronous interruption request register ASIRQ32 is set. Then the 1:1 collation is carried out by a comparator 33 between the register 32 and a device number register CPDNR31 under processing with the correspondence of device numbers. In this case, the bit corresponding to the device 4 of the register 31 is turned on to block an asynchronous interruption #0. Thus the asynchronous interruption request of a device which is under processing is inhibited temporarily. This can decrease the number of the asynchronous interruption.


Inventors:
ANZAI ICHIROU
Application Number:
JP14553083A
Publication Date:
February 26, 1985
Filing Date:
August 09, 1983
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F13/12; G06F13/24; (IPC1-7): G06F13/12
Attorney, Agent or Firm:
Sadaichi Igita