PURPOSE: To reduce the generating frequencies of data overrun by delivering a data transfer request added with the priority according to the using state of a data buffer.

CONSTITUTION: When a channel control part 3 accepts a data transfer request fetches the data within a buffer, the transfer byte number obtained at that time point is delivered to a bus 101 and added to the output of a register 44 by an arithmetic circuit 42. Then an arithmetic output signal 107 is selected by a selector 43 for replacement of the contents of the register 44. Thus the contents of the register 44 always show the number of idle bytes within the buffer. Then the high-order two bits of the register 44 are changed in four steps according to the idle areas with the buffer. That is, said two bits are equal to '00' with a ≤1/4 idle area, '01' with a 1/4W2/4 idle area, '10' with a 2/4W3/4 idle area and '11' with a ≥3/4 idle area respectively. Therefore, the output of a decoder 45 can transmit the transfer requests added with priorities by four steps of outputs AWD according to the idle state of the buffer to the part 3.