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Title:
CHANNEL SELECTION DEVICE
Document Type and Number:
Japanese Patent JPS63194408
Kind Code:
A
Abstract:

PURPOSE: To stabilize a PLL operation over entire reception channels, by damping the higher harmonic of the output of a fixed frequency divider by a first low-pass filter, passing the output of a second low-pass filter through a programmable frequency divider performing the phase comparison of the output of the programmable frequency divider and a reference frequency signal, and obtaining a desired oscillation frequency by correcting tuning potential.

CONSTITUTION: A Chebyshev type low-pass filter 13 with five stages is constituted by arranging coils 112 and 115 and capacitances 113 and 114 in a printed board 119, and with a through capacitor 110 arranged in a tuner cabinet 118. The fundamental wave output level of the filter 13 is amplified to a level to operate the programmable frequency demultiplier 14 at an amplifier 20. The phase comparison of the output signal with the signal of a reference oscillator 16 is performed at a phase comparator and charge pump circuit 15. And by returning the output signal to a voltage controlled oscillator VCO18 setting the potential smoothed at a smoothing low-pass filter 17 as the tuning potential, it is possible to set a desired VCO frequency.


Inventors:
USUI AKIRA
Application Number:
JP2772187A
Publication Date:
August 11, 1988
Filing Date:
February 09, 1987
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03J5/02; H04B15/04; (IPC1-7): H03J5/02; H04B15/04
Domestic Patent References:
JPS593625B21984-01-25
Attorney, Agent or Firm:
Tomoyuki Takimoto (1 person outside)



 
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