Title:
METHOD FOR MEASURING IMPURITY CONCENTRATION IN SEMICONDUCTOR ELEMENT
Document Type and Number:
Japanese Patent JP3156778
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To measure the concentration and distribution of an impurity near a p-n junction where a depletion layer is formed in a no-bias state.
SOLUTION: A forward bias voltage is applied across ohmic p-electrodes 107 and 109 and an AuGe n-electrode 101. The bias voltage is made nearly equal to the impurity diffusing potential near a p-n junction in a no-bias thermally balanced state. While the forward bias voltage is applied, a reverse bias voltage is applied across a Schottky electrode 108 and the n-electrode 101. The concentration distribution in a p-clad layer is measured by finding the relation between the reverse bias voltage and the depletion layer capacity immediately below the Schottky electrode 108.
Inventors:
Masayoshi Sumino
Application Number:
JP32543698A
Publication Date:
April 16, 2001
Filing Date:
November 16, 1998
Export Citation:
Assignee:
NEC
International Classes:
H01L21/66; H01L33/30; H01L33/38; H01L33/40; H01S5/00; H01S5/06; H01S5/30; (IPC1-7): H01L21/66; H01L33/00; H01S5/30
Domestic Patent References:
| JP5326664A | ||||
| JP6290941A | ||||
| JP52108771A |
Attorney, Agent or Firm:
Nobuyuki Kaneda (2 others)
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