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Title:
CHARGE TRANSFER DELAY CIRCUIT
Document Type and Number:
Japanese Patent JPS6125315
Kind Code:
A
Abstract:

PURPOSE: To decrease the effect of 1/f noise generated at a charge transfer delay element by applying signal processing at the input and output sides of the charge transfer delay element.

CONSTITUTION: An input circuit 1 and an output processing circuit 3 are connected respectively to the input and output of a CCD delay circuit 2. When an input signal from a terminal 4 is given, the input processing circuit 1 applies frequency conversion to the input signal toward high frequencies. Thus, the signal band is separated from the low frequency band where the level of 1/f noise is high. After a band with high 1/f noise is eliminated by an output processing circuit 3, the signal is subject to frequency conversion into the original band. Through the processing above, the effect of the 1/f noise generated by a charge transfer delay circuit is decreased.


Inventors:
IKEDA YASUNARI
YUJI HIROFUMI
NAKANO HIROSHI
Application Number:
JP14561484A
Publication Date:
February 04, 1986
Filing Date:
July 13, 1984
Export Citation:
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Assignee:
SONY CORP
International Classes:
G11C27/04; H03H11/26; (IPC1-7): G11C27/04; H03H11/26
Attorney, Agent or Firm:
Masatomo Sugiura



 
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