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Patent Searching and Data


Title:
CHATTERING ELIMINATION CIRCUIT
Document Type and Number:
Japanese Patent JPH02162821
Kind Code:
A
Abstract:

PURPOSE: To reduce the number of components by charging and discharging a capacitor from a constant current source according to an input signal and comparing a voltage across the capacitor with a reference voltage so as to obtain an output.

CONSTITUTION: An output of a comparator 5 changes from a low to a high level at a chattering when an input signal changes from a high level to a low level, a transistor(TR) 14 is turned from ON to OFF and a TR 15 is turned from OFF to ON and the capacitor 9 is discharged by a constant current source 9 and the voltage across the capacitor 9 is decreased. Since the input signal is inverted at the chattering part in a short time, the capacitor 9 is charged by a constant current source 7 and the capacitor voltage is increased again. Thus, the voltage across the capacitor 9 is always higher than a voltage at a point B being a reference voltage and the output 4 of the comparator 6 is kept to a high level. Thus, since a counter detecting the chattering width is not in use, the circuit is integrated with a few components.


Inventors:
OTSUKA SHOICHIRO
Application Number:
JP31795688A
Publication Date:
June 22, 1990
Filing Date:
December 15, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K5/1254; H03K5/01; (IPC1-7): H03K5/01
Domestic Patent References:
JP61075637B
JPS4727448A
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)