PURPOSE: To realize a chattering elimination circuit recognizing as one signal even when a chattering consecutive time is continuous for one period of a clock signal or over by making a counter means to count the clock signal only when a signal including chattering is stable.

CONSTITUTION: The circuit is provided with a signal input terminal 1, a clock input terminal 2, a counter means 3 reset by an input signal (a) including chattering, counting number of clock signals (b) and outputting a control signal (c) when the number reaches a prescribed number, and a set reset flip-flop 4 controlled by the input signal (a) including chattering and the control signal (c) from the counter means 3. Thus, the counter means 3 acts like latching an output of a storage circuit 4 for a prescribed time after the input signal (a) including chattering is lost and even when the chattering consecutive time is longer than one period of the clock signal (b), one signal is recognized.