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Title:
CHATTERING PREVENTING CIRCUIT
Document Type and Number:
Japanese Patent JPS57197636
Kind Code:
A
Abstract:

PURPOSE: To prevent chattering with simple constitution by delaying a latch signal for setting an encoded output of an input signal from a key contact point to a flip-flop for a longer time than the chattering period of the key contact point.

CONSTITUTION: To an encoder 1, contact point information (a) of information S0WSn from a key contact point S is inputted, and its output (b) encoded in plural bits is applied to a flip-flop 6. To a gate circuit 3, an OR signal of the S0WSn and the output from a clock generating circuit 2 are applied. The output (d) from the gate circuit 3 triggers a monostable multivibrator 4 and with the rise of its output (e) a multivibrator 5 sends a latch signal (f) that is delayed for the time longer than the chattering period to the flip-flop 6. With this process, a buffer gate 7 is capable of receiving information that is not affected by chattering.


Inventors:
HASHIMOTO HIROSHI
Application Number:
JP8237881A
Publication Date:
December 03, 1982
Filing Date:
May 29, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F3/02; H03M11/02; (IPC1-7): G06F3/02
Domestic Patent References:
JP55144439B
JPS5419306A1979-02-14