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Patent Searching and Data


Title:
CHECK SYSTEM FOR MULTI-PROCESSOR SYSTEM
Document Type and Number:
Japanese Patent JPS63257837
Kind Code:
A
Abstract:

PURPOSE: To attain the check of memory content of all processors by using a bus connector and a DMA controller enabling to set an address and data word number externally by a specific data on a bus so as to use a check control program only.

CONSTITUTION: In detecting a data with a specific identifier on a data bus 10 by a bus connector 21, it is written in a register 25 and a DMA controller 22 applies direct memory access with a memory 23 accordingly. When a check exclusive processor 50 reads a data of a specific processor unit 20 connected to the bus 10, since the unit 20 returns a designated data onto the bus independently of the software by sending the data representing a processor identifier, a DMA address and a word count and a data representing the direction of data to the bus 10, the data is realized and checked by displaying onto a terminal 30 connected to the processor 50.


Inventors:
MURAKAMI SATOSHI
Application Number:
JP9286987A
Publication Date:
October 25, 1988
Filing Date:
April 15, 1987
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F11/16; G06F15/16; G06F15/177; G01R31/28; G11C29/00; G11C29/56; (IPC1-7): G01R31/28; G06F11/16; G06F15/16
Attorney, Agent or Firm:
Naotaka Ide