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Patent Searching and Data


Title:
CHECKING SYSTEM FOR INTEGRATED CIRCUIT REVERSE INSERTION OF INTEGRATED CIRCUIT TESTER
Document Type and Number:
Japanese Patent JPS5852581
Kind Code:
A
Abstract:

PURPOSE: To decide a reversely inserted state, by making a prescribed very small constant-current flow alternately by changing its polarity, between a VCC terminal and GND terminal, to which an IC to be tested is inserted, and measuring the inter-terminal voltage, in a tester for automatically testing an IC characteristic.

CONSTITUTION: Into a terminal VCC and GND of an IC tester 1, an IC2 to be tested is inserted. A program control part 8 sets a prescribed voltage value, for instance, 0.7V to a setting circuit part 6. Subsequently, the control part 8 instructs a constant-current source circuit 3 to make a prescribed very small constant-current in the forward direction to a constant current source control part 5. In this case, a voltage measuring part 4 measures voltage between VCC and GND terminals in the tester 1, and sends it out to a comparing part 7. The comparing part 7 compares it with a set value of the circuit 6, and sends its result to the control part 8. Subsequently, the control part 8 instructs the control part 5 to make a prescribed very small current flow in the backward direction, and the same comparison as above is executed. The control part 8 decides whether an IC to be tested is in a reversely inserted state or not, from a result of comparison of the comparing part 7 in case when the very small constant-current has been made to flow in the forward direction and also in the backward direction.


Inventors:
AIZAWA AKIRA
Application Number:
JP15103381A
Publication Date:
March 28, 1983
Filing Date:
September 24, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G01R31/04; G01R31/28; G01R31/316; (IPC1-7): G01R31/28
Attorney, Agent or Firm:
Sadaichi Igita