Title:
ON CHIP BIAS GENERATOR
Document Type and Number:
Japanese Patent JPS5911662
Kind Code:
A
Abstract:
An improved on-chip bias generator for producing a negative bias for the substrate of a VLSI FET chip for reducing the body effect and for increasing circuit speed. The improvement comprises active FETs to rectify a ring oscillator square wave output, thereby reducing the voltage losses in the rectifier and increasing the amount of voltage delivered to the substrate.
Inventors:
HOODAI TORUONGU
Application Number:
JP11026983A
Publication Date:
January 21, 1984
Filing Date:
June 21, 1983
Export Citation:
Assignee:
XEROX CORP
International Classes:
H01L27/04; G05F3/20; H01L21/822; H03K17/687; H03K19/094; (IPC1-7): H01L27/04; H01L29/78; H03K17/687; H03K19/094
Attorney, Agent or Firm:
Asamura Akira
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