Title:
CHROMA SIGNAL PROCESSING UNIT
Document Type and Number:
Japanese Patent JP3133658
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To easily match a DC level of a B-Y signal with that of an R-Y signal.
SOLUTION: The processing unit is provided with a PLL detection circuit 12, selection means 18, 19, a 1st hold means 20, a 2nd hold means 21, a voltage generating circuit 100, a 1st differential amplifier 24 receiving a B-Y signal detection output signal of a PLL detection circuit 12 and an output signal of the voltage generating circuit 100 being a DC voltage of the B-Y signal detection output signal and in which the DC components of the two inputs are cancelled, and a 2nd differential amplifier 25 receiving a R-Y signal detection output signal of the PLL detection circuit 12 and an output signal of the voltage generating circuit 100 being a DC voltage of the R-Y signal detection output signal and in which the DC components of the two inputs are cancelled.
Inventors:
Keijiro Ueki
Ikuo Ohsawa
Takashi Hata
Ikuo Ohsawa
Takashi Hata
Application Number:
JP24635695A
Publication Date:
February 13, 2001
Filing Date:
September 25, 1995
Export Citation:
Assignee:
Sanyo Electric Co., Ltd.
International Classes:
H04N9/64; H04N9/66; (IPC1-7): H04N9/66; H04N9/64
Domestic Patent References:
| JP5130633A | ||||
| JP391398A | ||||
| JP767133A | ||||
| JP1168179A | ||||
| JP965356A |
Attorney, Agent or Firm:
Masamasa Shibano