Title:
CIRCUIT ARRANGEMENT FOR ALLOCATING PROPER CHANNEL TIME SLOT
Document Type and Number:
Japanese Patent JPH01120923
Kind Code:
A
Abstract:
PURPOSE: To reduce the supply of interference pulses to a time-divided multiplex highway by inhibiting an output from a channel allocating device when feed voltage is supplied to the device and monitoring a synchronized state in operation together with a synchronizing signal and a plug-in position code. CONSTITUTION: When a plug-in module is inserted, a memory SP is set up by the capacitor voltage of an RC circuit at the time of supplying feed voltage U and an inhibition signal is suppied to a control circuit ST. Thus a time delay determined by the RC circuit is ended and a synchronizing pulse is supplied as a synchronizing signal S and the memory SP is reset by the edge part of the pulse S. Logic '1' is supplied to the 1st input terminal of the circuit ST in response to the reset. The supply of logic '1' satisfies a 1st matter for releasing the circuit ST. A synchronizing monitoring circuit SUE monitors a synchronizing state at the time of operation.
Inventors:
HAINTSU KAIRUHORUTSU
Application Number:
JP25217088A
Publication Date:
May 12, 1989
Filing Date:
October 07, 1988
Export Citation:
Assignee:
PHILIPS NV
International Classes:
H04J3/00; H04Q11/04; (IPC1-7): H04J3/00; H04L11/20
Domestic Patent References:
| JPS6085697A | 1985-05-15 |
Attorney, Agent or Firm:
Akihide Sugimura (1 outside)