Title:
【発明の名称】積の和を形成する回路配置
Document Type and Number:
Japanese Patent JPH08500690
Kind Code:
A
Abstract:
In processors, in particular digital signal processors, it often happens that products of a chain of pairs of data words must be summed, for example for correlation or convolution operations, in which each data word of each pair may only have one of both values +1 or -1. According to the invention, one data word of each pair is supplied to a summing/subtracting arrangement, instead of being supplied to a multiplier for forming a product, and determines whether the summing/subtracting arrangement carries out a summing or a subtracting operation. One input of the summing/subtracting unit receives the other data words of the pairs of data words and the other input is connected to the output of the accumulator register. A costly multiplier arrangement can thus be dispensed with, or when it is anyway available, it is not used, so that the processor dissipates less power.
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Inventors:
Bayer Alfred
Shuk Johannes
Weintool Dirk
Shuk Johannes
Weintool Dirk
Application Number:
JP51503593A
Publication Date:
January 23, 1996
Filing Date:
December 17, 1993
Export Citation:
Assignee:
Philips Electronics Nemrose Fennaught Shap
International Classes:
G06F7/00; G06F7/50; G06F7/509; G06F7/544; G06F17/10; (IPC1-7): G06F17/10; G06F7/00; G06F17/10
Attorney, Agent or Firm:
Akihide Sugimura (1 outside)