Title:
CIRCUIT BOARD AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JPH10126059
Kind Code:
A
Abstract:
To increase wiring efficiency in designing a layer face conductive pattern, and to thin a multilayer substrate.
A multilayer substrate 1 having a through hole 5 and first to fourth layer face conductive patterns 6 to 9 is provided. In the multilayer substrate 1, an annular conductive layer 10 extending around the through hole 5 and connected to the first and the second layer face conductive patterns 6 and 7 is buried, and an annular insulating layer 11 interposed between the conductive layer 10 and the through hole 5 is also buried.
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Inventors:
NAGASHIMA KEIJI
Application Number:
JP27255296A
Publication Date:
May 15, 1998
Filing Date:
October 15, 1996
Export Citation:
Assignee:
NEC CORP
International Classes:
H05K3/46; (IPC1-7): H05K3/46
Attorney, Agent or Firm:
Kihei Watanabe
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