Title:
CIRCUIT BOARD, METHOD FOR MANUFACTURING CIRCUIT BOARD, AND ELECTRONIC DEVICE
Document Type and Number:
Japanese Patent JP2018179578
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To realize a circuit board in which damage attributable to stresses occurring in a conductor pin connecting part is suppressed.SOLUTION: A probe card 1, which is a circuit board, includes, for example, a glass layer 52, a glass layer 51 provided thereon and having a resin part 51c, a conductor via 30 penetrating the resin part 51c, and a probe pin 40 that is a conductor pin provided on the conductor via 30 and on the resin part 51c. According to the probe card 1, when a terminal of a semiconductor element and the probe pin 40 are contacted under pressure when electrically inspecting the semiconductor element, stresses occurring in the root 41 of the probe pin 40 and its periphery are relieved by the resin part 51c and damage attributable to the stress is suppressed.SELECTED DRAWING: Figure 3
Inventors:
IWAI TOSHIKI
MIZUTANI DAISUKE
MIZUTANI DAISUKE
Application Number:
JP2017075049A
Publication Date:
November 15, 2018
Filing Date:
April 05, 2017
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G01R1/073; G01R31/26; H01L21/66
Attorney, Agent or Firm:
Takeshi Hattori