Title:
CIRCUIT FOR CUT-TOOTH SENSOR AND CLOCK-SIGNAL GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JP2567166
Kind Code:
B2
Abstract:
PURPOSE: To simplify the circuit and to decrease the cost by providing a frequency dividing means, two up counters, a clock generating means, a counter controlling means and two coincidence detecting means.
CONSTITUTION: A first up counter 3 and a second up counter 4 repeat counting operations, holding of the counted values and resetting in the reverse phase with respect to the switching signal from a frequency dividing means 2. Therefore, the value, which is counted in the section of a previous pulse signal, is held in the next section. The held counted value is shifted to the upper level by one bit and compared with the value of the other up counter. When there is a cut-tooth part, the switching signal is not changed during the period of three pulse signals. Therefore, the up counting is performed in the up counter in this state. The counted value becomes twice the counted value held in the other up counter. Coincidence is detected with first and second coincidence detecting means 7 and 8. Thus a cut-tooth signal is generated. Two up counters 3 and 4 and the means 7 and 8 perform complementary operations, and the cut-tooth part is detected.
Inventors:
YAMANO SHINICHI
Application Number:
JP25390091A
Publication Date:
December 25, 1996
Filing Date:
October 01, 1991
Export Citation:
Assignee:
FUJITSU TEN LTD
International Classes:
G01B7/30; G01B21/22; G01D5/244; G01D5/245; H03K23/00; (IPC1-7): G01B21/22; G01D5/244; G01D5/245; H03K23/00
Domestic Patent References:
| JP6420413A |
Attorney, Agent or Firm:
Aoki Akira (4 outside)