PURPOSE: To facilitate efficient and waste-free analysis in designing a standard cell type LSI even if it contains a CPU core having an abnormally long wiring length by a method wherein a wiring having a practical length is added to the load of a designated call to calculate a delay time.

CONSTITUTION: A circuit diagram data input means 1 which inputs a first circuit connection information corresponding to the circuit diagram data of an object circuit, a display means 2 which displays the first circuit connection information and a second circuit connection information which is obtained by renewing the first information, a cell name designating means 3 which designates a cell included in the first and second circuit interconnection information, a wiring length input means 4 which inputs the length of a wiring which is to be a load of the designated cell, a circuit delay calculating means 5 which adds the load of the wiring having the inputted length to the load of the designated cell to calculate the delay time of the cell, a circuit connection information writing means 6 which renews the first and second circuit connection information in accordance with an intermediate result and a final result including the delay time calculated by the means 5, a circuit connection information storing means 7 which stores the first and second circuit connection information, etc., are provided.