To perform correct data demodulation.

A clock is reproduced from a composite video signal, and a timing signal preparation circuit 22 generates a timing signal on the basis of the reproduced clock. Meanwhile, a signal sliced by a data slicer 18 is inputted to a data fetch circuit 20. The timing signal is used here to fetch data. A data decision circuit 24 decides whether the fetched data is correct, and when the data is not correct, the phase of the timing signal outputted from the circuit 22 is shifted.