To provide a design pattern capable of evaluating depending on the design conditions at a level requiring phase shift mask and a light proximity effect in manufacture a circuit of a wafer following the advanced microminiaturization of circuit wirings.

The design circuit pattern for testing semiconductor circuits comprises a test cell group 101 having two or more test cells of unit circuits designed under individual conditions by connecting switches to one end or both ends, a decoder 102 for specifying an evaluation test cell 103, one or more address pads 104 for inputting signals, an input pad 105 for inputting a signal to the test cell, an output pad 106 for fetching an output signal, one or more reference evaluation test cells 103 separate from the test cell group, a reference evaluation input pad 107 connected directly to one end of each reference evaluation test cell, and an output pad 108 connected directly to the other end.