To provide a circuit design supporting device, a method for designing a circuit, and a program, capable of effectively erasing any timing condition violation.

In an inspecting part 11, the propagation delay time of a signal in each path in a circuit is analyzed, and whether or not a predetermined success standard is fulfilled for each path is checked. In a ranking part 12, a violating path which does not fulfill the success standard is extracted from the check result, and cells are ranked in accordance with the number of same cells appearing on the violating path. In a circuit element displacing part 13, the cell appearing the most frequently on the violating path is preferentially selected from the ranking result, and the cell is displaced with a different kind of cell having an equivalent function and different drive capability, and the check of the propagation delay time is executed by the checking part 11. When any violating path which does not fulfill the success standard exists as the check result, the next cell appearing the most frequently is further selected, and the displacement of the cell and the check of the propagation delay time is repeated.