Title:
CIRCUIT DEVICE FOR EVERY WORD SERIAL-PARALLEL CONVERSION
Document Type and Number:
Japanese Patent JPH03139020
Kind Code:
A
Abstract:
PURPOSE: To satisfactorily operate the serial/parallel conversion of each word by converting an input bit sequence by a serial/parallel converter, providing a control circuit which indicates synchronizing offset from the word boundary of this sequence, and outputting bit words included in a parallel configuration. CONSTITUTION: This device is provided with a circuit which operates a work for re-constituting bit groups B1 , B2 and B3 of 8 bits or the like when complete words are continuously outputted by a serial/parallel converter 1 so as to be continuously outputted in a parallel configuration. This circuit includes only a delay circuit 3 which delays each bit group B1 continuously transmitted from the serial/parallel converter 1 only in one clock pulse period of an operating clock OC, and the 8 parallel outputs 6. Also, a multiple line 4 being 8 parallel lines validates a group 81 converted by the converter 1 without being delayed in the parallel configuration, and a selecting circuit 5 outputs the specific part of each bit group in the parallel configuration by 16 outputs 6 and 4 in this case.
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Inventors:
KAARUUARUBERUTO TOURUBAN
Application Number:
JP17761990A
Publication Date:
June 13, 1991
Filing Date:
July 06, 1990
Export Citation:
Assignee:
ALCATEL NV
International Classes:
H03M9/00; H04J3/06; (IPC1-7): H03M9/00
Attorney, Agent or Firm:
Takehiko Suzue (3 outside)