Title:
CIRCUIT DEVICE FOR FREQUENCY DIVISION
Document Type and Number:
Japanese Patent JPH0715321
Kind Code:
A
Abstract:
PURPOSE: To attain frequency division by an odd number by frequency-dividing programming whose frequency-division rate is odd into half, deriving another signal, and dividing the frequencies of the signal into two equal parts. CONSTITUTION: A PLL circuit is frequently used for the turning of a radio receiver, and provided with a controllable oscillator 1. A tuning voltage is supplied from a phase detector 2 to the oscillator 1, and an output signal S1 of the oscillator 1 is supplied to a frequency-divider 3. At that time, an output signal S2 of the frequency-divider 3 has the relation of a frequency-division rate whose setting can be adjusted for the signal S1. Then, odd or even frequency-division is operated by a down counter 5 depending on each output signal level. Then, when the value of the counter 5 started from each set value is turned into zero, a flip flop FF6 is triggered, and an output signal changes the level, and another frequency-division rate is set. Then, a frequency-division rate even/odd signal S3 is generated, and even when the frequency-division rate is odd, the frequency-division can be attained, and the frequencies can be successively and repeatedly divided into half.
Inventors:
JIYAHANIYAARU SHIYAHABADEI
Application Number:
JP947994A
Publication Date:
January 17, 1995
Filing Date:
January 31, 1994
Export Citation:
Assignee:
BLAUPUNKT WERKE GMBH
International Classes:
H03K23/00; H03K23/64; H03K23/68; H03L7/197; (IPC1-7): H03K23/64; H03K23/00
Attorney, Agent or Firm:
Toshio Yano (2 outside)
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