To enhance the phase resolution by providing a memory for temporarily storing a binary word, and the like.

A reference signal R is fed to the input terminal of a shift register 1 which is clocked by a master clock TM and a slave clock TS. In a digital differentiator 2 comprising a delay element, input signal and output signal of the delay element are processed logically through an AND gate. Output from a counter 3 driven by a clock signal T is inputted to a temporary memory 4 which receives a binary word Z currently appearing at the output end of the counter 3 and stores the binary word Z until a new binary word is received. The binary word stored in the memory 4 can be taken out from the output end thereof and an upper position MSBs of the output binary word B, indicative of the phase difference between the reference signal R and the clock signal T is formed. Furthermore, the least significant bit LSB of the output binary word B is formed by the output from an FF7 connected with the output end of another shift register 5 being clocked reversely.