Title:
FORMATTING/DEFORMATTING CIRCUIT FOR DIGITAL DATA
Document Type and Number:
Japanese Patent JP2552102
Kind Code:
B2
Abstract:
PURPOSE: To separately execute the operation of the formatting/deformatting of digital data from a digital signal processor, and to decrease a required time and the consumption of a power at the time of the formatting/deformatting, related with the formatting deformatting circuit of the digital data.
CONSTITUTION: This circuit is constituted of a data RAM 50 which stores data for formatting, a program ROM 60 which stores a program for controlling the generation of an address, an address generating and parallel/serial converting part 41 which generates the address and converts parallel data outputted from the data RAM 50 into serial data, a data storing part 42 which stores the serial data outputted from the address generating and parallel/serial converting part 41, and a data outputting part 43 which divides and outputs data serially outputted from the data storing part 42 by prescribed bit units.
Inventors:
TE UON KUN
Application Number:
JP10106095A
Publication Date:
November 06, 1996
Filing Date:
April 25, 1995
Export Citation:
Assignee:
ERU JII DENSHI KK
International Classes:
G06F5/00; H03M9/00; (IPC1-7): G06F5/00
Attorney, Agent or Firm:
Takashi Ishida (3 others)