Title:
CIRCUIT FACILITATING COMMUNICATION OF DIGITAL SIGNAL
Document Type and Number:
Japanese Patent JPH08251003
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To convert a voltage level between circuits constituted by different technologies by transmitting a 2nd voltage level from a means which converts a 1st voltage level to a necessary circuit which is needed for operation. SOLUTION: The input signal from a circuit 10 reaches a line 14 and is received by the drain electrode of an N type device 32, which has a power source of 2.5 V connected to its gate electrode. When the receive signal is at low level, a series transistor 32 passes it to the input of a receiver, which processes and outputs the signal to a line 16. When the receive signal is at high level, on the other hand, the device 32 limits the passage of the input signal to the value obtained by subtracting the threshold value of the device 32 from the gate voltage. This limit voltage is applied to the input of the receiver 38 and put in the level range needed for the CMOS technology implemented in the circuit 12. Then one input terminal of a differential receiver 34 is connected to the source electrode of the device 32 and the other is connected to a set reference voltage.
Inventors:
TAI KEIO
SACHIYAJITSUTO DEYUTSUTA
TAI KUOKU GUUIEN
SAN DOAN TORIN
ERUROIDO ANDORE UOORUZU
SACHIYAJITSUTO DEYUTSUTA
TAI KUOKU GUUIEN
SAN DOAN TORIN
ERUROIDO ANDORE UOORUZU
Application Number:
JP884596A
Publication Date:
September 27, 1996
Filing Date:
January 23, 1996
Export Citation:
Assignee:
IBM
International Classes:
H03K19/00; H03K19/0175; H03K19/018; H03K19/0185; (IPC1-7): H03K19/0175; H03K19/00; H03K19/018
Attorney, Agent or Firm:
Kiyoshi Goda (2 outside)
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