Title:
CIRCUIT AND METHOD FOR CONFIRMATION OF WRITE STATE OF FLASH MEMORY DEVICE
Document Type and Number:
Japanese Patent JPH0629494
Kind Code:
A
Abstract:
PURPOSE: To make control gate voltage to be dead by comparing directly by a sense amplifier using equal resistances connected with a memory cell and a first adjustable reference device and generating a potential showing current. CONSTITUTION: This circuit extends within a memory cell 10 and the other memory cells in the line, and it is fitted to the gate of memory cell within the line. A line decoder selects a word line 12 in an array. A column in the array is also selected by a column decoder. Thus, a memory cell 10 is connected to a sense amplifier 30 through a line route 41. When a gate potential is applied to the word line 12, a current is generated according to the quantity of its charge. As a result, a circuit which generates a voltage independent substantially to working temperature change and gate voltage, is formed.
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Inventors:
GUREGORII II ATOUTSUDO
OOUEN DABURIYU JIYANGUROSU
NIIRU AARU MIIRUKU
BURANISURABU BUAJITSUKU
OOUEN DABURIYU JIYANGUROSU
NIIRU AARU MIIRUKU
BURANISURABU BUAJITSUKU
Application Number:
JP33941691A
Publication Date:
February 04, 1994
Filing Date:
November 29, 1991
Export Citation:
Assignee:
INTEL CORP
International Classes:
G11C17/00; G11C16/28; G11C16/34; G11C29/00; G11C29/12; G11C29/50; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L27/115; G11C16/06; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Masaki Yamakawa
Next Patent: 燃料噴射装置