To precisely obtain a lock frequency without using an envelope signal.

This PLL lock frequency counting circuit is provided with a PLL part 39-1 for generating a delay phase clock and a phase-lead clock with respect to a reproduction clock generated by a PLL circuit, a lock detection part 39-2 which detects the unlocked state of a PLL circuit when the difference between the delay phase clock and the phase-lead clock exceeds a prescribed value, and which detects the locked state of the PLL circuit when the difference between the delay phase clock and the phase-lead clock does not exceed the prescribed value, and a counting part 39-3 which is initialized in the unlocked state, starts counting reproduction clocks when the PLL circuit comes into the locked state, and outputs a counter value when the counter value becomes full as a lock frequency signal.