Title:
CIRCUIT AND METHOD FOR DETECTING DEFECT IN INTEGRATED CIRCUIT ARRAY
Document Type and Number:
Japanese Patent JP3904642
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To easily perform an IDDQ test by providing a logic circuit and the like having a pair of first and second NAND gates and the like in a decoding circuit.
SOLUTION: All conductors on every other line of an array are connected to a first voltage, other conductors on every other line of an array are connected to a second voltage, a current between the first voltage and the second voltage is measured (step a), when a current does not exceed a first limit value, processing is finished. When a current exceeds a first limit value, about not whole array but a first half and a second half of an array, conductors of all lines of a half of an array being in not testing are connected to a second voltage, and the above mentioned step (a) is independently repeated. When a current exceeds the second limit value in a half of the array, all lines are connected to the second voltage, the step (a) is repeated for each quarter of the array. When a current exceeds a third limit value in a quarter of the array, the same step is repeated for a part of the array which can be divided by 2 until sufficient information about defect can be obtained.
Inventors:
Harvey Jay Stiegler
Stephen Bu. Kruzenz
Stephen Bu. Kruzenz
Application Number:
JP32040196A
Publication Date:
April 11, 2007
Filing Date:
November 29, 1996
Export Citation:
Assignee:
Texas Instruments Incorporated
International Classes:
G01R31/28; G11C29/02; G11C29/04; G11C29/50; (IPC1-7): G11C29/00; G01R31/28
Domestic Patent References:
| JP5074197A |
Attorney, Agent or Firm:
Hideto Asamura
Hajime Asamura
Kuniaki Shimizu
Hayashi Zouzo
Hajime Asamura
Kuniaki Shimizu
Hayashi Zouzo