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Patent Searching and Data


Title:
CIRCUIT AND METHOD FOR DETECTING DELAY PROFILE
Document Type and Number:
Japanese Patent JP2000059332
Kind Code:
A
Abstract:

To accurately detect a delay profile in simple configuration by finding the correlation of an input signal and a delayed signal by delaying the input signal for a valid symbol period, and detecting the delay profile by differentiating an integrated signal which is formed by integrating a correlation signal outputted from a correlation means.

The input OFDM signal of a radio carrier or intermediate frequency(IF) band is converted to the complex OFDM signal of a base band by a quadrature demodulation circuit 10. One of complex OFDM signals is inputted to an input L of a correlation circuit 12 and the other signal is inputted to a delay circuit 11. The delay circuit 11 outputs the input signal after delaying it for one valid symbol period. The output of the delay circuit 11 is inputted to an input 2 of the correlation circuit 12 and the correlation with a signal not through the delay circuit 11 is calculated. The output signal of the correlation circuit 12 is inputted to an integration circuit 13, integrated for the symbol period and outputted later. The output of the integration circuit 13 is inputted to a differentiation circuit 14, differentiating calculation is performed and based on the calculated result, a delay profile detecting signal is outputted.


Inventors:
FUKUMORI HIROYUKI
Application Number:
JP22732098A
Publication Date:
February 25, 2000
Filing Date:
August 11, 1998
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04J11/00; H04L7/00; (IPC1-7): H04J11/00; H04L7/00
Attorney, Agent or Firm:
Nobuo Takahashi (3 outside)