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Title:
CIRCUIT AND METHOD FOR SIGNAL TRANSMISSION
Document Type and Number:
Japanese Patent JPH11266158
Kind Code:
A
Abstract:

To reduce the maximum value and the average of the number of bits which change at the sometime, in the transmission of a logical signal.

This device is equipped with a logical circuit 100, which converts a logical signal of n bits into m pairs (m is an integer equal to one or larger) of a group of logical signals, where only k bits (k is an integer equal to one or larger) change, a transmission line for transmitting the m pairs of logical signals, where only the k bits change, and a logical circuit 103 which converts the m pairs of logical signals, where only k bits change into a logical signal of the original n bits. Thus, for the maximum value of the number of changing bits has the product of k and m as an upper limit. Also, when the product of k and m is less than n/2, the average number of changing bits can be reduced also.


Inventors:
MIKI YOSHIO
Application Number:
JP6648898A
Publication Date:
September 28, 1999
Filing Date:
March 17, 1998
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03M5/06; H03M5/00; H03M7/14; (IPC1-7): H03M5/06; H03M7/14
Attorney, Agent or Firm:
Ogawa Katsuo



 
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