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Title:
CIRCUIT FOR PARALLEL CONNECTION OF TRANSISTOR
Document Type and Number:
Japanese Patent JPS5746514
Kind Code:
A
Abstract:

PURPOSE: To reduce the leakage inductance, by connecting primary windings of current transformers in series to emitters of transistors and by connecting secondary windings in series successively with the same polarity to form a close circuit.

CONSTITUTION: If an amitter current Ie1 of a transistor (TR) Q1 is increased and an emitter currents Ie2 and Ie3 of TRs Q2 and Q3 are reduced, Ie1>nIs (the current flowed to secondary windings Ns1∼Ns3), Ie2<nIs and Ie3<nIs<nIs becomes true in respective balancer current transformers T1, T2 and T3, and voltages e1, e2 and e3 are induced in respective primary windings NP1, NP2 and NP3. The voltage e1 makes the bias of the TRQ1 shallow and reduces the emitter current. Voltages e2 and e3 make the bias of TRs Q2 and Q3 deep and increases the emitter current.


Inventors:
WATANABE KIYOMI
Application Number:
JP12277880A
Publication Date:
March 17, 1982
Filing Date:
September 04, 1980
Export Citation:
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Assignee:
ORIGIN ELECTRIC
International Classes:
H03F3/68; (IPC1-7): H03F3/68
Domestic Patent References:
JP42006845A