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Patent Searching and Data


Title:
CIRCUIT FOR PREVENTION OF DAMAGE DUE TO ERRONEOUS INSERTION OF PANEL
Document Type and Number:
Japanese Patent JPH02311126
Kind Code:
A
Abstract:

PURPOSE: To prevent the application of primary power supply to an erroneously inserted circuit panel, and to display the erroneous insertion of said circuit panel by connecting the two pins of a connector on insertion, lowering applied voltage at both ends of the coil of a relay to voltage lower than the primary power supply of a power supply slot and bringing said relay to the state of non-operation.

CONSTITUTION: When the connector C2 of a circuit panel 22 is inserted erroneously to the connector C1 of a power supply slot 10, the pins p1, p2 of the connector C2 are connected by the series circuit of a resistor R for the voltage drop of a display means 221 in the circuit panel 22 and a diode LED for display, voltage at both ends of the coil L of a relay 11 is brought to voltage lower than the primary power supply of the power supply slot 10 by the resistor R and the relay 11 is brought to the state of non-operation, and the contacts t1, t2 of the relay 11 are turned OFF, thus preventing the supply of the primary power supply to the circuit panel 22, then displaying the erroneous insertion of the circuit panel 22 by the diode LED.


Inventors:
WATANABE SATOSHI
Application Number:
JP13390289A
Publication Date:
December 26, 1990
Filing Date:
May 26, 1989
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H05K7/14; H02H11/00; (IPC1-7): H02H11/00; H05K7/14
Attorney, Agent or Firm:
Sadaichi Igita