Title:
CIRCUIT FOR PROTECTING INPUT TERMINAL OF MOS IC
Document Type and Number:
Japanese Patent JPS5233486
Kind Code:
A
Abstract:
A circuit arrangement for the protection of inputs of integrated MOS circuits against excessive voltages, for example as a consequence of static charges, includes a first circuit means connected to the MOS circuit and having two bypass circuits reacting at different input voltage values and having a high-ohmic compensating resistance, and second circuit means is connected ahead of the first circuit and comprises a bypass circuit and a high-ohmic compensating resistance.
Inventors:
HAINRITSUHI KESURAA
Application Number:
JP10719876A
Publication Date:
March 14, 1977
Filing Date:
September 07, 1976
Export Citation:
Assignee:
SIEMENS AG
International Classes:
H03F1/52; H01L21/822; H01L27/02; H01L27/04; H01L27/06; H01L29/78; H02H9/04; H03F1/42; (IPC1-7): H01L27/04; H01L29/78; H03F1/00