Title:
CIRCUIT FOR RECEIVING AND DEMODULATING DATA SIGNAL
Document Type and Number:
Japanese Patent JPS6454808
Kind Code:
A
Abstract:
PURPOSE: To attain cost reduction by making a 2nd clock signal asynchronous with a 3rd clock signal and setting the 3rd clock signal to the integer relation with a 1st clock signal through 1st and 2nd frequency dividing means. CONSTITUTION: A high frequency sampling clock is 40 frequency divided 27-29 to low frequency sampling clocks for driving a signal gain stage 19 by a programmable timer, and is frequency divided 42 to a lower frequency at a fixed rate for supplying a clocking signal to a band filter 15. Based on the programmed down frequency division of the high frequency clock 40, the input of the clock to the gain stage 19 is made asynchronous with the band filter 15. However, the gain stage 19 is always set in the integer relation with an antialiasing fielder(AAF) 17 so as to achieve edge synchronism between the AAF 17 and the gain stage. Thus, an inexpensive programmable clock can be provided.
Inventors:
POORU HAASUTO
TOOMASU GURATSUDO
TOOMASU GURATSUDO
Application Number:
JP10980788A
Publication Date:
March 02, 1989
Filing Date:
May 02, 1988
Export Citation:
Assignee:
SILICON SYSTEMS INC
International Classes:
H04L27/38; H03H19/00; H04L25/03; (IPC1-7): H03H19/00; H04L27/00
Attorney, Agent or Firm:
Masaki Yamakawa (2 outside)