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Patent Searching and Data


Title:
CIRCUIT FOR SELECTING OPTIMUM CLOCK PHASE
Document Type and Number:
Japanese Patent JPS6460121
Kind Code:
A
Abstract:

PURPOSE: To always execute identification with an optimum phase even when a distance between both stations is changed and to cause the distance between the both stations not to be limited in the propagation delay time of one bit and to remove the limit of a service area by always keeping the phase of a clock to identify reception data to be optimum.

CONSTITUTION: Since the reception data are inputted to D-FFs 23 and 24 to be continuously connected and a sampling is executed by the clock to be two fold-multiplied, the reception data are successively held with being delayed for a 1/2 period. Since a signal to successively hold the reception data with a timing to be different in the 1/2 period by inputting the output of the D-FFs 23 and 24 to a D-FF 25 and executing the sampling with an internal clock, the decidence is detected by an exclusive 'or' circuit 26. When the decidence is detected, since a switching to the separate clock whose phase is different at 90° the phase of the clock to identify the receiving data goes to be suitable. Thus, even when the distance between radio devices is changed, the reception the data can be identified and received with the optimum phase and the limit concerning the service area can be removed.


Inventors:
TAKEDA YUKIO
KANEKO YOSHIAKI
KIMURA AKIHIKO
Application Number:
JP21739387A
Publication Date:
March 07, 1989
Filing Date:
August 31, 1987
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04L7/02; (IPC1-7): H04L7/02
Attorney, Agent or Firm:
Kugoro Tamamushi (1 outside)