To obtain a circuit simulation apparatus capable of predicting the occurrence of the latch up and location thereof.

A layout parameter extractor 100 extracts possible latch up elements which may cause the latch up from a layout drawing to create circuit connection information including circuit-like connection information of the latch up elements. A simulator 200 simulates a semiconductor integrated circuit including the latch up elements as circuit elements to output simulation result D3. A latch up judging unit 3 predicts whether the latch up element is latched up or not, from the simulation result D3. Thus, this circuit simulation can reduce, if used, the developing time about the latch up of semiconductor integrated circuits.