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Title:
回路シミュレーション装置、回路シミュレーション方法
Document Type and Number:
Japanese Patent JP5373652
Kind Code:
B2
Abstract:

To reproduce electric characteristics of a MOS transistor at high level of accuracy.

A circuit simulation apparatus including a graphic information generation means, a parameter correction amount calculation means and a circuit simulation means performs circuit simulation by the following method. In the method, a middle point in the longitudinal direction of a channel on a boundary between a channel region and an STI region is specified. When a gate width direction is set as a vertical direction, the middle point is set as an origin and a distance between a MOS transistor and a diffusion layer adjacent to the MOS transistor is set as a vertical direction adjacent diffusion layer distance, the vertical direction adjacent diffusion layer distance is specified as a function of a vertical direction distance to be changed according to a position X in the longitudinal direction of the channel. A multiplication expression multiplying the function of the vertical direction adjacent diffusion layer distance and a weighting function is generated and a parameter correction amount is calculated on the basis of the multiplication expression.

COPYRIGHT: (C)2011,JPO&INPIT


Inventors:
Kenta Yamada
Application Number:
JP2010012525A
Publication Date:
December 18, 2013
Filing Date:
January 22, 2010
Export Citation:
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Assignee:
Renesas Electronics Corporation
International Classes:
G06F17/50
Domestic Patent References:
JP2006178907A
Attorney, Agent or Firm:
Minoru Kudo