PURPOSE: To eliminate an erroneous detection in a circuit, for a test mode, which is used to simultaneously test output data signals from a plurality of memory regions in a semiconductor memory.

CONSTITUTION: The negation of a logical product is formed, by a NAND circuit, of two input data signals D1, D2 which are input to input terminals 101, 103, and a logical sum is formed, by a NOR circuit 107 and an inverter 110, of complementary signals DB1, DB2. The negation of the logical sum of logically operated results is formed by a NOR circuit 111, a signal which is composed of the product of the data signal D1 and of the negation of its complementary signal DB1 is formed, and the signal is applied to a gate for a transistor 113. In addition, in a NAND circuit 108, a NOR circuit 106, an inverter 109 and a NOR circuit 112, signals which are composed of individual data signals and of the product of their complementary signals are formed, the signals are applied to a transistor 114, and an output is obtained from an output terminal 115.