Title:
Circuit
Document Type and Number:
Japanese Patent JP5934773
Kind Code:
B2
Abstract:
One object is to provide a boosting circuit whose boosting efficiency is enhanced. Another object is to provide an RFID tag including a boosting circuit whose boosting efficiency is enhanced. A node corresponding to an output terminal of a unit boosting circuit or a gate electrode of a transistor connected to the node is boosted by bootstrap operation, so that a decrease in potential which corresponds to substantially the same as the threshold potential of the transistor can be prevented and a decrease in output potential of the unit boosting circuit can be prevented.
Inventors:
Yutaka Shionoiri
Suhei Suo
Suhei Suo
Application Number:
JP2014241670A
Publication Date:
June 15, 2016
Filing Date:
November 28, 2014
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H02M3/07; G06K19/07; G11C5/14; G11C16/06; H01L21/822; H01L27/04; H01L29/786
Domestic Patent References:
| JP2005304285A | ||||
| JP2009171692A | ||||
| JP62065375A |