PURPOSE: To achieve a higher sampling accuracy at a low level of an analog signal by setting a sampling period of a sampling/holding circuit on the higher- order bit side of a serial digital data.

CONSTITUTION: A first serial digital data S1 is supplied to a D/A converter 1 and when a latch signal S2 attains an H level at a time t5, the data S1 is loaded and converted into an analog signal S3 at a time t6 while the analog signal S3 is latched. The signal S3 is supplied to one of analog switches 3 through a buffer amplifier 2. When a sample signal S4 attains a high level as outputted from a sample signal control means 6 at three bits from the higher- order side of a second serial digital data S1 supplied at a time t7, the switch 3 is turned ON. Under such a condition, a capacitor 4 connected to the other end of the switch 3 is charged with an analog signal S3 supplied through the amplifier 2, thereby achieving a sampling accuracy at a low level of the analog signal.