To provide a class-D amplifier capable of preventing clipping without delay.

A pulse width modulation circuit 1 generates a PWM pulse PC of which pulse width is modulated by an input signal Vin. An output buffer circuit 2 performs switching drive to a load L in accordance with an input pulse PD. A fixed pulse generating circuit 3 generates fixed pulses PA and PB with predetermined pulse widths at timing synchronous with a generation timing of the PWM pulse PC. An input control circuit 4 supplies the PWM pulse PC to the output buffer circuit 2 as the input pulse PD at generation timing of the fixed pulse PA or PB if the PWM pulse PC of the pulse width wider than that of the fixed pulse PA or PB is generated. If the PWM pulse PC with such a wide pulse width is not generated, the fixed pulse PA or PB is supplied to the output buffer 2 as the input pulse PD.