Title:
CLOCK ABNORMALITY DETECTOR
Document Type and Number:
Japanese Patent JP2015005198
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To enable more stable detection of clock abnormality between a transient operation including a clock uncertain section at the time of power source activation or the like to a stationary operation.SOLUTION: A clock abnormality detector includes: a first counter 21a which counts a first clock signal; a second counter 21b which counts a second clock signal; a first abnormality determination circuit 22a which determines that a second clock is in abnormality if the count value of the second counter does not reach a predetermined value A2 when the count value of the first counter reaches a predetermined value B1 larger than a predetermined value A1; and a second abnormality determination circuit 22b which determines that a first clock is in abnormality if the count value of the first counter does not reach the predetermined value A1 when the count value of the second counter reaches a predetermined value B2 larger than the predetermined value A2.
Inventors:
MORIMOTO NOBUAKI
Application Number:
JP2013130853A
Publication Date:
January 08, 2015
Filing Date:
June 21, 2013
Export Citation:
Assignee:
ASAHI KASEI DENSHI KK
International Classes:
G06F1/04; H03K5/19
Attorney, Agent or Firm:
Woods Tetsuya
Tanaka 秀てつ
Tanaka 秀てつ
Previous Patent: 復調回路、受信器及び復調方法
Next Patent: SERVER DEVICE, PRODUCT INFORMATION NOTIFICATION SYSTEM, PRODUCT INFORMATION NOTIFICATION METHOD AND ...
Next Patent: SERVER DEVICE, PRODUCT INFORMATION NOTIFICATION SYSTEM, PRODUCT INFORMATION NOTIFICATION METHOD AND ...