Title:
データ再生システムにおけるクロック調整装置及び光ディスク装置
Document Type and Number:
Japanese Patent JP3597433
Kind Code:
B2
Abstract:
A clock adjustment apparatus for adjusting a phase of a clock signal based on a phase error thereof is provided in a data reproduction system which samples a readout signal from a recording medium in synchronism with the clock signal, and reproduces data in accordance with a Viterbi algorithm by using sampled values of the readout signal. The recording medium is recorded with the data modulated in accordance with a recording rule of a predetermined partial response characteristic. The clock adjustment apparatus includes a phase error calculation circuit which calculates the phase error of the clock signal based on the sampled values of the readout signal.
Inventors:
Kenichi Hamada
Satoshi Furuta
Masakazu Taguchi
Satoshi Furuta
Masakazu Taguchi
Application Number:
JP36155099A
Publication Date:
December 08, 2004
Filing Date:
December 20, 1999
Export Citation:
Assignee:
富士通株式会社
富士通周辺機株式会社
富士通周辺機株式会社
International Classes:
G11B20/14; G11B20/10; H04L7/027; (IPC1-7): G11B20/14; H04L7/027
Domestic Patent References:
| JP11328874A | ||||
| JP9007304A |
Attorney, Agent or Firm:
Tadahiko Ito