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Patent Searching and Data


Title:
CLOCK COMPARATOR CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS59125420
Kind Code:
A
Abstract:

PURPOSE: To prevent the interruption of a comparator from being ceased even if the value of a clock comparator register varies during scanning operation by confirming and setting, etc. the contents of a TOD (Time of DAY) timer and a clock comparator register by a coincidence circuit.

CONSTITUTION: This system performs data processing by using a scan loop system and the coincidence circuit 3 compares the contents of the TOD timer 1 with the contents of the clock comparator register 2 wherein a desired value is set by the instruction of the timer; when they coincide with each other, an FF4 is set to start a microprogram. Further, a scan control circuit 5 which scans the register 3 and another register 6, etc., is provided, and the FF4 is set when its scanning operation is completed to start a microprogram interruption.


Inventors:
MIYAJIMA SHIGERU
HAMAOKA SHIYOUSUKE
Application Number:
JP23406982A
Publication Date:
July 19, 1984
Filing Date:
December 30, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F1/14; G06F9/48; G06F11/22; (IPC1-7): G06F1/04; G06F9/46
Attorney, Agent or Firm:
Kyotani Shiro