PURPOSE: To suppress a data error at its minimum by counting up data error detecting signals during a fixed period, comparing the current value with the counted value obtained before one period and controlling the delay of an input clock signal based on the counted value corresponding to the compared result.

CONSTITUTION: A resampling clock 1 from a TV receiving part is delayed by a delay line 2 with a tap so that the error ratio of sound data is minimized. On the other hand, a counter 7 counts up error correction detecting signals 6 generated during the fixed period and the counted value is stored in an FF group 8 and then stored in an FF group 9 at the succeeding timing. The contents of the FF groups 8, 9 are compared by a comparator 10, and if A>B, the compared output is turned to 'H', a toggle FF 11 is triggered and a reversible counter 15 executes up-counting by the Q output of the FF 11. The output of the counter 15 addresses a demultiplexer 3, one of the outputs of the delay line 2 is selected and sent to a PCM decoder part as an output 5. When the counted value of the counter 7 is less than a prescribed value, an OR circuit 14 stops the counter 15.