To provide a clock creation circuit, and its method which can create an output clock signal CLKreq which has a frequency "freq" between a frequency fref/A of a demultiplied clock signal CLK1 and a frequency fref/(A+1) of a demultiplied clock signal CLK2.
A clock demultiply circuit 12 selectively creates the demultiplied clock signals CLK1, CLK2. A discrete value correction circuit 14 controls the clock demultiply circuit 12, if C<D, repeats C times to create the clock signal CLK2 once, and create (Q-1) times of the clock signal CLK1, and creates R times of the clock signal CLK1, if C>D, repeats D times to create the clock signal CLK1 once, and create (Q-1) times of the clock signal CLK2, and creates R times of the clock signal CLK2. A, B, C are natural numbers, and satisfy freq=fref/(A+C/B). D=B-C, Q is a quotient of B/C in case of C<D, and a quotient of B/D in a case of C>D.
MATSUSE SHUSAKU
UEDA MAKOTO
Yoshihiro City
Takeshi Ueno
Hidetoshi Ueba