Title:
クロックアンドデータリカバリ回路
Document Type and Number:
Japanese Patent JP4335586
Kind Code:
B2
Abstract:
A clock and data recovery circuit, for tracking frequency-modulated input data, comprises a phase detector for receiving a data signal and a synchronous clock signal, detecting a phase delay or a phase advance, and outputting an UP 1 /DOWN 1 signal, first and second integrators for integrating the UP 1 /DOWN 1 signal and outputting an UP 2 /DOWN 2 signal and an UP 3 /DOWN 3 signal, respectively, a pattern generator for receiving the UP 3 /DOWN 3 signal from the second integrator to output an UP 4 /DOWN 4 signal, a mixer for receiving the UP 2 /DOWN 2 signal from the first integrator and the UP 4 /DOWN 4 signal from the pattern generator and generating an UP 5 /DOWN 5 signal for output, and a phase interpolator for interpolating the phase of an input clock signal based on the UP 5 /DOWN 5 signal from the mixer, for output are provided. A clock signal output from the interpolator is fed back to the phase detector as the clock.
Inventors:
Aoyama Morishige
Application Number:
JP2003166712A
Publication Date:
September 30, 2009
Filing Date:
June 11, 2003
Export Citation:
Assignee:
NEC Electronics Corporation
International Classes:
H03L7/08; H03D13/00; H03K5/15; H03L7/06; H03L7/081; H03L7/089; H03L7/093; H03L7/107; H03L7/113; H04L7/033
Domestic Patent References:
| JP2002190724A | ||||
| JP2001273048A | ||||
| JP2000285605A | ||||
| JP10145228A |
Attorney, Agent or Firm:
Kato Asamichi